Timepix4 chipboard and readout concept
- NázevTitle
- Timepix4 chipboard and readout conceptTimepix4 chipboard and readout concept
- Druh výsledkuResult type
- Článek v časopiseJournal article
- AutořiAuthors
- O. Ruzicka, P. Burian, P. Broulim, B. Bergmann, P. Smolyanskiy
- Klíčová slovaKeywords
- Data acquisition concepts, Digital electronic circuits, Electronic detector readout concepts (solid-state), Modular electronics
- KonferenceConference
- 20th Anniversary Trento Workshop on Advanced Silicon Radiation Detectors (Trento, Italy, 2025-02-04)
- DOIDOI
- 10.1088/1748-0221/20/06/C06074
- Časopis / citaceJournal / citation
- Journal of Instrumentation 20(06), C06074 (2025) · ISSN 1748-0221
- RokYear
- 2025
- JazykLanguage
- eng
- ZáznamyRecords
- ProjektProject
- Identifikace částic v experimentech fysiky vysokych energií a ve vesmíru s pokročilými detekčními systémyParticle identification in high-energy physics experiments and space with advanced detection systems
- CitovánoCited by
- 2 (OpenAlex)
- Citace ke staženíDownload citation
- TXT · BibTeX
AbstraktAbstract
This paper presents a modular readout and chipboard concept developed for the Timepix4 hybrid pixel detector, a high-performance ASIC featuring 448 x 512 pixels and sub-nanosecond timing resolution. Building on the success of Timepix3, Timepix4 supports both frame-based and data-driven acquisition modes with data rates up to 3.6 MHits/mm2/s and 195 ps time binning. The chip can be integrated via wire-bonding or Through-Silicon-Via (TSV) technology, allowing full four-side tiling for scalable detector arrays. The modular chipboard system, consisting of a detector module and a baseboard, simplifies power delivery and data transmission using a single 12 V supply and Ethernet-style cabling. A commercial FPGA-based readout supports up to four detectors with Gigabit Ethernet and PCIe interfaces. The concept was successfully validated at CERN SPS with heavy-ion beams, demonstrating system stability and high data integrity. Ongoing development focuses on enhanced power and cooling systems, multi-chip integration, and improved software support for advanced experimental setups.
This paper presents a modular readout and chipboard concept developed for the Timepix4 hybrid pixel detector, a high-performance ASIC featuring 448 x 512 pixels and sub-nanosecond timing resolution. Building on the success of Timepix3, Timepix4 supports both frame-based and data-driven acquisition modes with data rates up to 3.6 MHits/mm2/s and 195 ps time binning. The chip can be integrated via wire-bonding or Through-Silicon-Via (TSV) technology, allowing full four-side tiling for scalable detector arrays. The modular chipboard system, consisting of a detector module and a baseboard, simplifies power delivery and data transmission using a single 12 V supply and Ethernet-style cabling. A commercial FPGA-based readout supports up to four detectors with Gigabit Ethernet and PCIe interfaces. The concept was successfully validated at CERN SPS with heavy-ion beams, demonstrating system stability and high data integrity. Ongoing development focuses on enhanced power and cooling systems, multi-chip integration, and improved software support for advanced experimental setups.